The present invention relates in general to semiconductor memories and in particular to a novel flash memory array architecture and methods of operation of the same.
FIG. 1 is a simplified diagram of a conventional flash memory array. The array includes a matrix of flash memory cells 100 connected as shown to a group of bit lines BL0-BLM, a group of word lines WL0-WLN, and a common or global source line GSL that receives source voltage VSS. The most common variety of flash memories today employs channel hot electron (CHE) for programming and negative gated Fowler-Nordhiem (FN) tunneling for erase. The CHE programming normally programs 1, 2, 4, 8 or 16 cells at a time and involves multiple program and program verify steps. During the programming sequence voltages are applied to the various terminals of each cell until the cell threshold voltage VT rises above the minimum programming threshold voltage VTPmin. A typical condition for CHE programming of cell 00 is, e.g., word line 0 (WL0)=10volts, bit line 0 (BL0)=5 volts, WLI-N=0 volts, BL1-M=0 volts. This type of CHE programming can result in a well-controlled and narrow VTP distribution across the array.
Negative gated FN tunneling erase uses multiple erase and erase verify steps to ensure that the threshold voltage for all cells is less than the maximum erase threshold voltage (i.e., VT&lt;VTEmax). As shown in FIG. 1, conventional flash memory arrays use a global source line GSL that connects to the source terminal of all cells within an array. Thus, during erase, all cells with a common source line are erased at the same time. This is commonly referred to as bulk erase or sector erase. A typical erase condition is, e.g., WL0-N=-10 volts, BL0-M=Float, and GSL (VSS)=4 volts. The negative gated FN tunneling erase in conventional flash memories suffers from a number of drawbacks. To ensure that the slowest cell in the array is fully erased, the erase operation normally involves multiple erase steps. In the case of those cells that are already erased prior to the start of another erase operation, a new erase cycle may cause the cell to be depleted, lowering the threshold voltage into the negative range. This effect, which is commonly referred to as over-erasure, can result in functional failure. To prevent over-erasure, all the cells in the array to be erased are first programmed before the actual erase operation begins. This is referred to as preprogramming. Preprogramming is a very time consuming process (e.g., 1 .mu.s per cell) and increases the array erase time significantly.
Another problem with this type of bulk erase is poor control over VTE distribution. To increase the cell current and device speed, it is desirable to have a VTEmax that is as low as possible. Even with a preprogramming step, the simultaneous and repeated erasing of all of the cells in the array results in wide distribution of VTE among the cells across the array. A wide VTE distribution, however, places a lower limit on the value of VTEmax since VTEmin must not become negative. FIG. 2 illustrates a typical distribution for VTE and VTP for a conventional FN-erase/CHE-program type flash memory. In this example, VTEmin is set at zero and VTEmax at 2 volts. There is a two volt sensing margin and a 1 volt data retention margin, placing VTPmin at 5 volts. With a 2 volt wide VTE distribution, targeting a lower VTEmax would result in negative VTEmin which would be unacceptable.
There is therefore a need for a flash memory device that does not suffer from the problems associated with over-erasure and wide VTE distribution.